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8-bit FAST Microcontrollers Family ver 2.08
OVERVIEW
Document contains brief description of DF6811 core functionality. The DF6811 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6811 soft core is binary-compatible with the industry standard 68HC11 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. DF6811 has FAST architecture that is 3.8 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral function. There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has implemented three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a nonmaskable interrupt if illegal opcode is detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the
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DF6811 IP Core especially attractive for automotive and battery-driven applications. The DF6811 have built in the development support features designed into DF6811. The LIR signal is intended as a debugging aid. This signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (disassemble) instructions from the display of a logic analyzer. DF6811 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
CPU FEATURES
FAST architecture, 3,8 times faster than the original implementation Software compatible with industry standard 68HC11 10 times faster multiplication 16 times faster division 64 bytes of remapped System Function Registers space (SFRs) Up to 16M bytes of Data Memory De-multiplexed Address/Data Bus to allow easy connection to memory Two power saving modes: STOP, WAI
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User programmable External Data Memory Write and Read pulses between 1 to 8 clock periods Fully synthesizable, static synchronous design with no internal tri-states No internal reset generator or gated clock Scan test ready Technology independent HDL source code Core can be fully customized
16-bit Compare/Capture Unit
Three independent input-capture functions Five output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring
DESIGN FEATURES
ONE GLOBAL SYSTEM CLOCK SYNCHRONOUS RESET The DF6811 has 3 reset vectors sources, which easy identify a cause of system reset. ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED BEFORE INTERNAL USE DATA MEMORY: The DF6811 can address up to 16M bytes of Data Memory via the function interconnect signals. The 64 bytes of Data Memory in every 64k page is reserved for the Function Registers. Extra DPP (Data Page Pointer) register is used for segments swapping. Data Memory can be implemented as synchronous or asynchronous.
8-bit Pulse accumulator
Two major modes of operation Simple event counter Gated time accumulation Clocked by internal source or external pin
Full-duplex UART - SCI
Standard Nonreturn to Zero format (NRZ) 8 or 9 bit data transfer Integrated baud rate generator Enhanced receiver data sampling technique Noise, Overrun and Framing error detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up

from IDLE condition
Three SCI related interrupts
PERIPHERALS
The peripherals listed below are not implemented in standard configuration of DF6811. They can be integrated in Core as a option. Four 8-bit I/O Ports Interrupt Controller
20 interrupt sources 17 priority levels Dedicated Interrupt vector for each interrupt
SPI - Master and Slave Serial Peripheral Interface
Supports speeds up 1/4 of system clock Mode fault error Write collision error Software selectable polarity and phase of se-
rial clock SCK
System errors detection Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
Interrupt generation
source
Main16-bit timer/counter system
16 bit free running counter Four stage programmable prescaller Timer clocked by internal source Real Time Interrupt All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl
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DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance

* SPI Interface * Support for IDIV Instruction * Support for FDIV Instruction * Support for MUL Instruction * Support for DAA Instruction
-
used unused used unused used unused used unused used unused
LICENSING
Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for
VHDL,

Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support
CONFIGURATION
The following parameters of the DF6811 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code.
* Data Memory size * Data Memory wait-states * Power saving STOP mode * WATCHDOG Timer * Timer system * Compare Capture channels * Pulse Accumulator * PORTS A, B, C, D * SCI - UART Interface 64 kB 16 MB used (0-7) unused used unused used unused used unused used unused used unused used unused used unused
Verilog source code called HDL
Source
Encrypted,or plain text EDIF called Netlist
One Year license for
Encrypted Netlist only
Unlimited Designs license for
HDL Source Netlist
Upgrade from
HDL Source to Netlist Single Design to Unlimited Designs
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PINS DESCRIPTION
PIN clk rst datai[7:0] ufrdatai[7:0] por copi cmf datai[7:0] ufrdatai[7:0] irq xirq portai[7:0] portbi[7:0] portci[7:0] portdi[7:0] cap1,2,3 pai rxd si mi scki ss datao[7:0] addr[23:0] ramwe ramoe ufrwe ufroe lir halt cme copo cmp1,2,3,4,5 cmp1z,2,3,4,5 portxo[7:0] ddrx[7:0] cmp1,2,3,4,5 cmp1z,2,3,4,5 txd so mo scko sckz ACTIVE Low Low Low Low * Low Low * Low High High * Low Low Low Low Low Low High High Low * High * High Low High High * High TYPE input input input input input input input input input input input input input input input input input input input input input input output output output output output output output output output output output output output output output output output output output output output DESCRIPTION Global system clock Global system reset External memory bus input UFRs data bus input Power on reset vector fetch COP timeout vector fetch Clock monitor fail vector fetch External memory bus input UFRs data bus input Interrupt input Non-maskable interrupt input Port A input Port B input Port C input Port D input Capture inputs Pulse accumulator input SCI receiver data input SPI slave input SPI master input SPI clock input SPI slave select Data memory & UFR bus output Data memory & FR address bus Memory write enable Memory output enable UFRs write enable UFRs output enable Load instruction register Halt clock system (STOP inst.) Clock monitor enable WATCHDOG timeout output Compare outputs Disconnect output compare Port A, B, C, D output Port A, B,C,D data direction control Compare outputs Disconnect output compare SCI transmitter data output SPI slave output SPI master output SPI clock output Disconnect SPI clock output
SYMBOL
clk rst datai(7:0) ufrdatai(7:0) datao(7:0) addr(23:0) ramwe ramoe ufrwe ufroe lir halt cme copo portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cap1 cap2 cap3 cmp1 cmp2 cmp3 cmp4 cmp5 cmp1z cmp2z cmp3z cmp4z cmp5z txd so mo scko sckz
por copi cmf irq xirq portai(7:0) portbi(7:0) portci(7:0) portdi(7:0)
pai
rxd si mi scki ss
BLOCK DIAGRAM
Control Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages execution of STOP instruction and waking-up the processor from the STOP mode. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks.
* Kind of activity is configurable
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ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), Index registers X, Y and related logic such as arithmetic unit, logic unit, multiplier and divider.
clk rst
Opcode Decoder
ALU
external pins (IRQ and XIRQ) as well as from particular peripherals. The DF6811 peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized according to default arrangement (look at the table below) established during reset. However any one source may be elevated to the highest maskable priority position using HPRIO register. When interrupt condition occurs, an interrupt status flag is set to indicate the condition. and divider. Timer, Compare Capture & COP Watchdog - This timer system is based on a free-running 16-bit counter with a 4-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record the time when a selected transition is detected at a respective timer input pin. Five outputcompare functions are included for generating output signals or for timing software delays. Since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in greater detail. A programmable periodic interrupt circuit called RTI is tapped off of the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is loosely related to the main timer in that the clock input to the COP system (clk*217) is tapped off the free-running counter chain. The timer subsystem involves more registers and control bits than any other subsystem on the MCU. Each of the three input-capture functions has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. Additional control bits permit software to control the edge(s) that trigger each inputcapture function and the automatic actions that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications although it is not as
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por cmf copi cme halt lir irq xirq
Control Unit
RAM & SFR Control
datai(7:0) datao(7:0) addr(23:0) ramwe ramoe ufrwe ufroe portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cap1 cap2 cap3 cmp1 cmp2 cmp3 cmp4 cmp5 cmp1z cmp2z cmp3z cmp4z cmp5z
Interrupt Controller
copo
Watchdog Timer
I/O Ports
pai
Pulse Accumulator
rxd txd
SCI Unit
so si mo mi scko scki sckz ss
SPI Unit
Timer with Compare / Capture Unit
RAM & SFR Controller - Data Memory & SFR (Special Function Register) interface controls access into the internal and external program and data memories and special registers. It contains Stack Pointer (SP) register, INIT register (INIT), Data Page Pointer (DPP), Stretch register (ST) and related logic. Interrupt Controller - DF6811 extended IC has implemented 17-level interrupt priority control. The interrupt requests may come from
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efficient as dedicated hardware for some specific timing applications. and divider. SCI - The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The DF6811 resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multi-drop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag, this SCI also provides a transmit complete (TC) indication that can be used in applications with a modem. SPI Unit - it's a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. SPI automatically drives slave select outputs SSO[7:0], and address SPI slave device to
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exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master. Pulse Accumulator - This system is based on an 8-bit counter and can be configured to operate as a simple event counter or for gated time accumulation. Unlike the main timer, the 8-bit pulse accumulator counter can be read or written at any time (the 16-bit counter in the main timer cannot be written). Control bits allow the user to configure and control the pulse accumulator subsystem. Two maskable interrupts are associated with the system, each having its own controls and interrupt vector. The PAI pin associated with the pulse accumulator can be configured to act as a clock (event counting mode) or as a gate signal to enable a free-running E divided by 64 clock to the 8-bit counter (gated time accumulation mode). The alternate functions of the pulse accumulator input (PAI) pin present some interesting application possibilities. I/O Ports - All ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers have their corresponding data direction registers DDRA, DDRB, DDRC, DDRD to control ports data flow. It assures that all DF6811's ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. If any port pins are configured as output then data registers are driven out of those pins. Reads from port pins configured as input causes that input pin is read. If port pins is configured as output, during read data register is read. Writes to any ports pins not configured as outputs do not cause data to be driven out of those pins, but the data is stored in the output registers. Thus, if the pins later become outputs, the last data written to port will be driven out the port pins.
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OPTIONAL PERIPHERALS
There are also available an optional peripherals, not included in presented DF6811 Microcontroller Core. The optional peripherals, can be implemented in microcontroller core upon customer request. PWM - Pulse Width Modulation Timer
2 independent 8-bit PWM channels, concate-
FCHS - change sign FABS - absolute value
Floating-Point math coprocessor - IEEE754 standard single precision real, word and short integers
FADD, FSUB- addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM- compare FCHS - change sign FABS - absolute value FSIN, FCOS- sine, cosine FTAN, FATAN - tangent arcs tangent
nated on one 16-bit PWM channel
Software-selectable duty from 0% to 100% and
pulse period
Software-selectable polarity of output wave-
form
I2C bus controller - Master
7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation
PERFORMANCE
The following tables give a survey about the Core area and performance in the ASICs and Programmable Logic Devices after Place & Route (all CPU features and peripherals have been included):
Device ORCA 3T ORCA 4E ispXPGA Speed grade -7 -3 -5 Fmax 8 MHz 31 MHz 30 MHz
I2C bus controller - Slave
NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation
Core performance in LATTICE(R) devices
Area utilized by the each unit of DF6811 core in vendor specific technologies is summarized in table below.
Component CPU* Main Timer COM/CAP Watchdog Pulse Acc. SPI Interface UART - SCI I/O Ports Total area Area
[LC / PFU] [FFs]
Programmable Watchdog Timer Fixed-Point arithmetic coprocessor
Multiplication - 16bit * 16bit Division - 32bit / 16bit Division - 16bit / 16bit Left and right shifting - 1 to 31 bits Normalization
2300 / 340 83 / 14 501 / 86 72 / 13 48 / 9 135 / 24 326 / 60 157 / 28 3300 / 574
311 50 196 30 19 60 131 96 893
*CPU - consisted of ALU, Control Unit and Instruction Decoder, Bus Controller with support for 16MB RAM, External IRQ and XIRQ pin Interrupt Controller
Core components area utilization
Floating-Point arithmetic coprocessor IEEE-754 standard single precision
FADD, FSUB - addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM - compare All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl
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IMPROVEMENT
For user the most important is application speed improvement. The most commonly used arithmetic functions and theirs improvement are shown in table below.
Improvement was computed as {M68HC11 clock periods} divided by {DF6811 clock periods} required to execute an identical function. More details are available in core documentation
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 16-bit addition (immediate data) 16-bit addition (direct addressing) 16-bit addition (indirect addressing 16-bit subtraction (immediate data) 16-bit subtraction (direct addressing) 16-bit subtraction (indirect addressing Multiplication Fractional division Integer division Improvement 4 4 4 4 4 4 5,3 5 4,8 5,3 5 4,8 10 14,9 16.4
DF6811 FAMILY OVERVIEW
The main features of each DF6811X family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications.
Pulse accumulator * + Paged Data Memory space Compare\Capture SPI M/S Interface Motorola Memory Expansion Logic Interrupt sources
Watchdog Timer
Main Timer System
Real Time Interrupt
DF6811 DF6811CPU
+ optional * configurable
64k 64k
16M 16M
-
20 3
17 3
+
1* 1*
1* +
5/3* +
1* +
I\O Ports
Design
4 +
* + +
*
DF6811X family of High Performance Microcontroller Cores
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Interface for additional SFRs
Physical Linear memory space
Interrupt levels
Data Pointers
SCI (UART)
CONTACTS
For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: iinffo@dcd..pll n o@dcd p tel. fax : +48 32 282 82 66 : +48 32 282 74 37
Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iinffoUS@dcd..pll n oUS@dcd p tel. fax : +1 210 422 8268 : +1 210 679 7511
Distributors: MTC - Micro Tech Components GmbH AM Reitweg 15 89407 Dillingen, GERMANY
MTC n o@m c de e-mail : MTCiinffo@mttc..de
tel. : +49 9071 7945-0 fax : +49 9071 7945-20 Territory: Germany, Austria, Switzerland
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